Compilation flows are often accepted as black boxes. Based on the input code, their task is to produce an executable version of the process description. This translation is necessary for any compiled programming language and execution environment. Therefore, compilers generally accomplish the task of translating abstract descriptions into concrete machine instructions.
Whereas this procedure is frequently used by programmers for all different kinds of compiled languages, influencing the result is often limited to common compiler options, e. g., the specification of an optimization level. However, compiler development itself is a very interesting discipline of computer science. The availability of different possibilities to influence the translation process can improve not only the quality of a resulting implementation but also the process of development itself. For x86 processors, compilers usually offer a huge number of options while only very few are regularly taken into account (like the typically used ‘-O3’ option in, e. g., Intel's or GNU's compiler collections).
When dealing with more ‘exotic’ architectures, the situation is similar or even more pronounced. Different situations and different goals demand flexible configurability regarding ‘which direction a compiler should take’ to translate an input description into executable instructions or even synthesized hardware. This is especially the case if hard restrictions (like indispensable timing constraints) have to be respected in order to guarantee the correct functionality of a system. Under such circumstances, FPGAs or other reconfigurable hardware devices are often the architecture of choice. The straight implementation in hardware, paired with the option to renew this hardware implementation without the need to replace any hardware parts, make such devices more and more important, especially if frequent changes of the hardware design are anticipated or if only a small number of the hardware should be produced. The manufacturing of an ASIC design in small quantities is often much more expensive than integrating an appropriate reconfigurable equivalent (which has been produced in very large amounts). In the end, this relatively generic chip only has to be configured with the appropriate functionality. In this context, ‘placement’ is the part of the compile flow that assigns synthesized logic units to suitable positions on the architecture.